Ceramic via wafer-level packaging for MEMS

被引:0
|
作者
Heck, John M. [1 ]
Arana, Leonel R. [1 ]
Read, Bill [1 ]
Dory, Thomas S. [1 ]
机构
[1] Intel Corp, Microsyst Technol, Santa Clara, CA 95054 USA
关键词
D O I
10.1115/IPACK2005-73369
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
We will present a novel approach to wafer level packaging for micro-electro-mechanical systems. Like most common MEMS packaging methods today, our approach utilizes a wafer bonding process between a cap wafer and a MEMS device wafer. However, unlike the common methods that use a silicon or glass cap wafer, our approach uses a ceramic wafer with built-in metal-filled vias, that has the same size and shape as a standard 150 mm silicon wafer. This ceramic via wafer packaging method is much less complex than existing methods, since it provides hermetic encapsulation and electrical interconnection of the MEMS devices, as well as a solderable interface on the outside of the package for board-level interconnection. We have demonstrated successful ceramic via wafer-level packaging of MEMS switches using eutectic goldtin solder as well as tin-silver-copper solder combined with gold thermo-compression bonding. In this paper, we will present the ceramic via MEMS package architecture and discuss the associated bonding and assembly processes.
引用
收藏
页码:1069 / 1074
页数:6
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