Impact of Advanced Gate Stack Engineering On Low Frequency Noise Performances of Planar Bulk CMOS transistors

被引：0

作者：

Mercha, A. ^{[1
]}

Okawa, H. ^{[2
]}

Akheyar, A. ^{[3
]}

Simoen, E. ^{[1
]}

Nakabayashi, T. ^{[2
]}

Hoffmann, T. Y. ^{[1
]}

机构：

[1] IMEC, Kapeldreef 75, B-3001 Louvain, Belgium

[2] Panasonic, Kadoma, Osaka, Japan

[3] Infineon, Neubiberg, Germany

来源：

NOISE AND FLUCTUATIONS | 2009年 / 1129卷

关键词：

metal gate; Low-frequency noise; CMOS; high-k dielectrics; INTERFACIAL LAYER; N-MOSFETS; BEHAVIOR;

D O I：

暂无

中图分类号：

Q6 [生物物理学];

学科分类号：

071011 ;

摘要：

This paper discusses on the impact of gate stack engineering on the low-frequency noise performance of state-of-the-art deep submicron planar CMOS technologies. Focus is on the scaling of the Equivalent Oxide Thickness (EOT) in high-k gate oxides in combination with metal gates, requiring the implementation of cap layers. As will be shown, different trends in the LF noise can be observed, indicating that LF noise optimization is a complex interplay between the different gate stack components.

引用

页码：277 / +

页数：2

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