Power visualization, analysis, and optimization tools for FPGAs

This paper introduces the Low-Power Intelligent Tool Environment (LITE), an object oriented tool set designed for power visualization, analysis, and optimization. These tools leverage an established FPGA design environment, JHDL, that allows design logic and power utilization to be displayed, analyzed, and cross-probed simultaneously at a level of abstraction close to the design entry point. Circuit logic, FPGA architecture and power information are correlated to create accurate power prediction and estimation models. These models and power analysis tools can then be used to create power optimization algorithms. Power optimization algorithm development is supported through the use of tools to query and sort circuit characteristics and drop in COTS CAD tool compliant constraints. These constraints can be used to guide the COTS placement and routing tools to optimize for power.