16 Bit Power Efficient Carry Select Adder

被引：0
|
作者：
Gaur, Nidhi [1 ]
Mehra, Anu [1 ]
Kumar, Pradeep [1 ]
Kallakuri, Sankalp [2 ]
机构：
[1] Amity Univ Uttar Pradesh, Dept ECE, ASET, Noida, India
[2] Mando Softech India Ltd, Gurgaon, Haryana, India
来源：
2019 6TH INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND INTEGRATED NETWORKS (SPIN) | 2019年
关键词：
Carry Select Adder; zynq; 7000; FPGA; Han Carlson; Brent Kung; Weinberger architecture and Ling architecture;
D O I：
10.1109/spin.2019.8711565
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The paper presents a new and modified area and power efficient carry select adder is proposed using Weinberger architecture and it is compared for efficiency with modified Carry Select Adder using Han Carlson, Brent Krung, and Ling adder architectures along with conventional carry select adder. Carry Select Adder proposed here using Weinberger architecture turned out to be the best in terms of area and power. Simulations of all five adder architectures are performed in Xilinx Vivado tool version 14.4 and hardware implementations are performed on zynq 7000 FPGA board which uses 28nm technology.
引用
收藏
页码：558 / 561
页数：4
相关论文
共 50 条
  • [1] Power and Area Efficient Carry Select Adder
    Anagha, U. P.
    Pramod, P.
    [J]. PROCEEDINGS OF THE 2015 IEEE RECENT ADVANCES IN INTELLIGENT COMPUTATIONAL SYSTEMS (RAICS), 2015, : 17 - 20
  • [2] CMOS Implementation of Efficient 16-Bit Square Root Carry-Select Adder
    Akhter, Shamim
    Chaturvedi, Saurabh
    Pardhasardi, Kilari
    [J]. 2ND INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND INTEGRATED NETWORKS (SPIN) 2015, 2015, : 891 - 896
  • [3] Area and Power Efficient Carry-Select Adder
    Prasad, Govind
    Nayak, V. Shiva Prasad
    Sachin, S.
    Kumar, K. Lava
    Saikumar, Soma
    [J]. 2016 IEEE INTERNATIONAL CONFERENCE ON RECENT TRENDS IN ELECTRONICS, INFORMATION & COMMUNICATION TECHNOLOGY (RTEICT), 2016, : 1897 - 1901
  • [4] Low Power and Area Efficient Carry Select Adder
    Kumar, V. Nithish
    Raj, Pani Prithvi
    Lakshminarayanan, G.
    Sellathurai, Mathini
    [J]. JOURNAL OF LOW POWER ELECTRONICS, 2014, 10 (04) : 593 - 601
  • [5] A Power-Delay Efficient Carry Select Adder
    Katreepalli, Raghava
    Meruguboina, Drona
    Haniotakis, Themistoklis
    [J]. 2017 2ND INTERNATIONAL CONFERENCE FOR CONVERGENCE IN TECHNOLOGY (I2CT), 2017, : 1234 - 1238
  • [6] Design of Low Power and High Speed Modified Carry Select Adder for 16 bit Vedic Multiplier
    Prasad, Bhavani Y.
    Chokkakula, Ganesh
    Reddy, Srikanth P.
    Samhitha, N. R.
    [J]. 2014 INTERNATIONAL CONFERENCE ON INFORMATION COMMUNICATION AND EMBEDDED SYSTEMS (ICICES), 2014,
  • [7] 32 bit Power efficient Carry Select Adder Using 4T XNOR gate
    Rashmi, S. B.
    Oli, Veena
    [J]. PROCEEDINGS OF THE 2016 2ND INTERNATIONAL CONFERENCE ON APPLIED AND THEORETICAL COMPUTING AND COMMUNICATION TECHNOLOGY (ICATCCT), 2016, : 283 - 287
  • [8] AN EFFICIENT STRUCTURE OF CARRY SELECT ADDER
    Rajesh, A.
    Madhumalini, M.
    [J]. 2014 INTERNATIONAL CONFERENCE ON GREEN COMPUTING COMMUNICATION AND ELECTRICAL ENGINEERING (ICGCCEE), 2014,
  • [9] Implementation of an efficient 64-bit Carry Select Adder using Muxes
    Chandran, Rahul G.
    Saraswathi, N.
    [J]. 2014 INTERNATIONAL CONFERENCE ON ADVANCED COMMUNICATION CONTROL AND COMPUTING TECHNOLOGIES (ICACCCT), 2014, : 430 - 434
  • [10] Implementation and Comparison of VLSI Architectures of 16 Bit Carry Select Adder Using Brent Kung Adder
    Kumar, N. Udaya
    Sindhuri, K. Bala
    Teja, K. Durga
    Satish, D. Sai
    [J]. 2017 INNOVATIONS IN POWER AND ADVANCED COMPUTING TECHNOLOGIES (I-PACT), 2017,
12345