A low dead time vernier delay line TDC implemented in an actel flash-based FPGA

被引：0
|
作者：
Qin Xi [1 ,2 ]
Feng Changqing [1 ,2 ]
Zhang Deliang [1 ,2 ]
Zhao Lei [1 ,2 ]
Liu Shubin [1 ,2 ]
An Qi [1 ,2 ]
机构：
[1] Univ Sci & Technol China, State Key Lab Particle Detect & Elect, Hefei 230026, Peoples R China
[2] Univ Sci & Technol China, Dept Modern Phys, Hefei 230026, Peoples R China
来源：
NUCLEAR SCIENCE AND TECHNIQUES | 2013年 / 24卷 / 04期
关键词：
Time measurement; Vernier; Time-to-digital convertor; Double delay lines; Compensation; TO-DIGITAL CONVERTER; RESOLUTION;
D O I：
暂无
中图分类号：
TL [原子能技术]; O571 [原子核物理学];
学科分类号：
0827 ; 082701 ;
摘要：
In this paper, a high precision vernier delay line (VDL) TDC (Time-to-Digital Convertor) in an actel flash-based Field-Programmable-Gate-Arrays A3PE1500 is implemented, achieving a resolution of 16.4-ps root mean square value or 42-ps averaged bin size. The TDC has a dead time of about 200 ns while the dynamic range is 655.36 vs. The double delay lines method is employed to cut the dead time in half to improve its performance. As the bin size of the TDC is dependent on temperature, a compensation algorithm is adopted as temperature drift correction, and the TDC shows satisfying performance in a temperature range from -5 degrees C to +55 degrees C.
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页数：7
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