An integrated CMOS PLL for low-jitter applications

被引：10

作者：

Herzel, F ^{[1
]}

Fischer, G ^{[1
]}

Gustat, H ^{[1
]}

Weger, P ^{[1
]}

机构：

[1] IHP, D-15236 Frankfurt, Germany

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING | 2002年 / 49卷 / 06期

关键词：

D O I：

10.1109/TCSII.2002.802965

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This brief presents a fully integrated integer-N frequency synthesizer with a frequency-tuning range from 2.4 to 2.9 GHz and root-mean-square (rms) jitter below 2.5 ps over 350 MHz. The employed architecture using an inductance-capacitance (L-C) oscillator with two control inputs combines a wide tuning range with a low noise sensitivity. Potential applications include clock generation in microprocessors and clock recovery in fiberoptic receivers.

引用

页码：427 / 429

页数：3

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