Temporal partitioning for image processing based on time-space complexity in reconfigurable architectures

Temporal partitioning techniques are useful to implement large and complex applications, which can be split into partitions in FPGA devices. In order to minimize resources, each of these partitions can be multiplexed in an only FPGA area by reconfiguration techniques. These multiplexing approaches increase the effective area, allowing parallelism exploitation in small devices. However, multiplexing means reconfiguration time, which can cause impact on the application performance. Thus, intensive parallelism exploitation in massive computation applications must be explored to compensate such inconvenient and improve processes. In this work, a temporal partitioning technique is presented for a class of image processing (massive computation) applications. The proposal technique is based on the algorithmic complexity (area x time) for each task that composes the applications. Experimental results are used to demonstrate the efficiency of the approach when compared to the optimal solution obtained by exhaustive timing search.