Transient Overshoot of Sub-10nm Bulk FinFET ESD Diodes with S/D Epitaxy Stressor

被引：0

作者：

Chen, Shih-Hung ^{[1
]}

Linten, Dimitri ^{[1
]}

Hellings, Geert ^{[1
]}

Simicic, Marko ^{[1
]}

Chiarella, Thomas ^{[1
]}

Eyben, Pierre ^{[1
]}

Kubicek, Stefan ^{[1
]}

Rosseel, Erik ^{[1
]}

Hikavyy, Andriy ^{[1
]}

Horiguchi, Naoto ^{[1
]}

机构：

[1] IMEC, Kapeldreef 75, B-3000 Leuven, Belgium

来源：

2019 41ST ANNUAL EOS/ESD SYMPOSIUM (EOS/ESD) | 2019年

关键词：

D O I：

10.23919/eos/esd.2019.8870001

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

New process options in CMOS technology scaling often result in degradation of ESD device performance. TCAD simulations bring an in-depth look at the impact of S/D epitaxy process options with channel strain engineering on CDM-time domain turn-on transient overshoot of ESD diodes in next generation bulk FinFET and GAA technologies.

引用

页数：8

共 28 条

[1] Towards High Performance Sub-10nm finW Bulk FinFET Technology
Chiarella, T.
Kubicek, S.
Rosseel, E.
Ritzenthaler, R.
Hikavyy, A.
Eyben, P.
De Keersgieter, A.
Ragnarsson, L-A.
Kim, M. -S
Chew, S. -A
Schram, T.
Demuynck, S.
Cupak, M.
Rijnders, L.
Dehan, M.
Horiguchi, N.
Mitard, J.
Mocuta, D.
Mocuta, A.
Thean, A. V-Y.
[J]. 2016 46TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC), 2016, : 131 - 134
[2] FinFET based SRAMs in Sub-10nm domain
Mohammed, Mahmood Uddin
Nizam, Athiya
Ali, Liaquat
Chowdhury, Masud H.
[J]. MICROELECTRONICS JOURNAL, 2021, 114
[3] ESD nMOSFETs in Advanced Bulk FinFET Technology With Dual S/D Epitaxy
Chen, Wen-Chieh
Chen, Shih-Hung
Chiarella, Thomas
Hellings, Geert
Linten, Dimitri
Groeseneken, Guido
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2022, 69 (09) : 5357 - 5362
[4] A SUB-10NM U-SHAPE FINFET DESIGN WITH SUPPRESSED LEAKAGE CURRENT AND DIBL EFFECT
Zhou, Wei-Chao
Wang, Peng-Fei
Zhang, David Wei
[J]. 2015 CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE, 2015,
[5] On the design of p-channel step-FinFET at sub-10nm node: A parametric analysis
Padhi, Santosh Kumar
Narendar, Vadthiya
Nishad, Atul Kumar
[J]. MICROELECTRONICS JOURNAL, 2022, 126
[6] Scalpel Soft Retrace Scanning Spreading Resistance Microscopy for 3D-carrier profiling in sub-10nm WFIN FinFET
Eyben, P.
Chiarella, T.
Kubicek, S.
Bender, H.
Richard, O.
Mitard, J.
Mocuta, A.
Horiguchi, N.
Thean, A. V-Y.
[J]. 2015 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2015,
[7] CDM-Time Domain Turn-on Transient of ESD Diodes in Bulk FinFET and GAA NW Technologies
Chen, S. -H.
Linten, D.
Hellings, G.
Simicic, M.
Kaczer, B.
Chiarella, T.
Mertens, H.
Mitard, J.
Mocuta, A.
Horiguchi, N.
[J]. 2019 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2019,
[8] First Demonstration of OxRRAM Integration on 14nm FinFet Platform and Scaling Potential Analysis towards Sub-10nm Node
Xu, Xiaoxin
Yu, Jie
Gong, Tiancheng
Yang, Jianguo
Yin, Jiahao
Dong, Da Nian
Luo, Qing
Liu, Jing
Yu, Zhaoan
Liu, Qi
Lv, Hangbing
Liu, Ming
[J]. 2020 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2020,
[9] Process, design rule, and layout co-optimization for DSA based patterning of sub-10nm Finfet devices
Mitra, Joydeep
Torres, Andres
Pan, David Z.
[J]. EMERGING PATTERNING TECHNOLOGIES, 2017, 10144
[10] Simulation of source-to-drain (S/D) tunneling in sub-10nm DG MOSFETs with WKB method
Jiang, B
Zhang, DW
Zheng, QT
Tian, LL
Yu, ZP
[J]. 2003 5TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2003, : 1361 - 1364

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