A Fully-Automated Flow for ITAR-Free Rad-Hard Atmel FPGAs

In recent years, use of FPGAs has been gaining more momentum for space applications as there are cases where using them can significantly reduce developments costs and time. In order to ensure correct operation in space, they have to be rad-hard, but most of such components are subject to ITAR. Atmel is the only provider for ITAR-free rad-hard FPGAs, but the default development flow provided leaves much to be desired. The contribution of this work is two-fold: First of all, we present a fully automated flow which improves the usability of the default development now provided by Atmel, while requiring only a bare minimum of configuration 14 each design. Secondly, we show how to extend this flow in order to integrate external programs which can be used as in-place substitutions of steps of the default flow. Our experiments show that the proposed flow can significantly boost both the productivity of the designers and the QoR of the final implementations.