Energy estimation and optimization of embedded VLIW processors based on instruction clustering

Aim of this paper is to propose a methodology for the definition of ail instruction-lovel energy estimation framework for VLIW (Very Long Instruction Word) processors. The power modeling methodology is the key issue to define an effective energy-aware software optimisation strategy for state-of-the-art ILP (Instruction Level Parallelism) processors. The methodology, is based on an energy model for VLBV processors that exploits instruction clustering to achieve an efficient and fine grained energy estimation. The approach aims at reducing the complexity of the characterization problem for VLIW processors from exponential, with respect to the number of parallel operations in the same very long instruction, to quadratic, with respect to the number of instruction clusters. Furthermore, the paper proposes a spatial scheduling algorithm based oil a low-power reordering of the parallel operations within the same long instruction. Experimental results have been carried out oil the Lx processor, a 4-issue VLIW core jointly designed by HPLabs and STMicroelectronics. The results have shown ail average error of 1.9% between the cluster-based estimation model and the reference design, with a standard deviation of 5.8%. For the Lx architecture, the spatial instruction scheduling algorithm provides ail average energy saving of 12%.