Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology

被引：58

作者：

Flandre, D

Viviani, A

Eggermont, JP

Gentinne, B

Jespers, PGA

机构：

[1] Lab. de Microélectronique, Univ. Catholique de Louvain

[2] Univ. Catholique de Louvain, Louvain-la-Neuve

[3] NTT Headquarters, Tokyo

[4] Ctro. Nac. de Microelectronica, Barcelona

[5] Lab. de Microélectronique, Louvain-la-Neuve

[6] Res. Assoc. Natl. Fund for Sci. Res., FNRS

[7] Ecole Royale Militaire, Brussels

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1997年 / 32卷 / 07期

关键词：

circuit stability; circuit synthesis; CMOS analog integrated circuits; design automation; operational amplifiers; silicon-on-insulator technology;

D O I：

10.1109/4.597291

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A systematic study of the gain-boosted regulated-cascode operational transconductante amplifier (OTA) CMOS stage is presented. Symbolic analysis is used first to describe the pole-zero behavior and second to propose design criteria for optimal settling time. A synthesis procedure based on the ''gm/ID'' methodology is considered further on for quick optimization of the architecture based on the de open-loop gain, transition frequency, and settling time specifications. Practical design cases are finally discussed.

引用

页码：1006 / 1012

页数：7

共 6 条

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[5] Design and analysis of folded cascode OTAs using Gm/Id methodology based on flicker noise reduction
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