A 16-Channel Fully Configurable Neural SoC With 1.52 μW/Ch Signal Acquisition, 2.79 μW/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI

被引：15

作者：

Zeinolabedin, Seyed Mohammad Ali ^{[1
]}

Schuffny, Franz Marcus ^{[1
]}

George, Richard ^{[1
]}

Kelber, Florian ^{[1
]}

Bauer, Heiner ^{[1
]}

Scholze, Stefan ^{[1
]}

Hanzsche, Stefan ^{[1
]}

Stolba, Marco ^{[1
]}

Dixius, Andreas ^{[1
]}

Ellguth, Georg ^{[1
]}

Walter, Dennis ^{[1
]}

Hoeppner, Sebastian ^{[1
]}

Mayr, Christian ^{[1
]}

机构：

[1] Tech Univ, D-01069 Dresden, Germany

来源：

IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS | 2022年 / 16卷 / 01期

基金：

欧盟地平线“2020”;

关键词：

Biomedical electronics; biomedical signal processing; digital integrated circuits; energy efficiency; neural recording system; implantable devices; accelerator architectures; spike sorting; unsupervised learning; MICROELECTRODE ARRAY; PROCESSOR; ELECTRODES; PROBE; ARM;

D O I：

10.1109/TBCAS.2022.3142987

中图分类号：

R318 [生物医学工程];

学科分类号：

0831 ;

摘要：

With the advent of high-density micro-electrodes arrays, developing neural probes satisfying the real-time and stringent power-efficiency requirements becomes more challenging. A smart neural probe is an essential device in future neuroscientific research and medical applications. To realize such devices, we present a 22 nm FDSOI SoC with complex on-chip real-time data processing and training for neural signal analysis. It consists of a digitally-assisted 16-channel analog front-end with 1.52 mu W/Ch, dedicated bio-processing accelerators for spike detection and classification with 2.79 mu W/Ch, and a 125 MHz RISC-V CPU, utilizing adaptive body biasing at 0.5 V with a supporting 1.79 TOPS/W MAC array. The proposed SoC shows a proof-of-concept of how to realize a high-level integration of various on-chip accelerators to satisfy the neural probe requirements for modern applications.

引用

页码：94 / 107

页数：14