Implementation of 4-Bit Data Transmission for Accessing SD Card with FPGA Embedded Soft Processor

被引：0

作者：

Ujjan, Gul Munir ^{[1
,2
]}

Malik, Abdul ^{[1
]}

Ahmed, Shakil ^{[3
]}

Abdullah, Mohd Zaid ^{[1
]}

机构：

[1] Univ Sains Malaysia, Sch Elect & Elect Engn, Engn Campus, George Town 14300, Malaysia

[2] NED Univ Engn & Technol, Comp & Informat Syst Engn Dept, Univ Rd, Karachi 75270, Sindh, Pakistan

[3] Sir Syed Univ Engn & Technol Karachi, Dept Comp Engn, Karachi, Pakistan

来源：

PROCEEDINGS OF 2019 4TH INTERNATIONAL CONFERENCE ON INTELLIGENT INFORMATION TECHNOLOGY (ICIIT 2019) | 2019年

关键词：

4-bit/1-bit SD mode; FPGA; NIOS-II processor; Altera DE-4 board; Stratix IV;

D O I：

10.1145/3321454.3321475

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Secure Digital (SD) cards being removable, non-volatile and flash memory in nature, are highly preferred for use in FPGA based systems as secondary storage. Currently most FPGA developers prefer 1-bit SD mode data transmission as a mean to access the SD card due to the complexity of 4-bit serial design. Hence, the speed is significantly compromised. This paper discusses the design and implementation of a firmware for 4-bit SD mode data transmission. A simple hardware application based on switches, buttons, memory and SD card interface is used to illustrate the functionality of proposed firmware, particularly the generation of the required control signal for data access. Meanwhile the Verilog HDL is used for hardware design while the software control is coded in C language. The system is implemented on Altera DE-4 board with FPGA Stratix IV GX EP4SGX230 and 32-bit NIOS-II embedded soft processor. In terms of data throughput the new firmware is 80 % much faster compared to a standard 1-bit data transmission when accessing a single block of data.

引用

页码：67 / 72

页数：6

共 4 条

[1] A 4-BIT JOSEPHSON DATA PROCESSOR CHIP
HATANO, Y
YANO, SI
MORI, H
YAMADA, H
HIRANO, M
KAWABE, U
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1989, 24 (05) : 1312 - 1316
[2] 4-bit CNN Quantization Method With Compact LUT-Based Multiplier Implementation on FPGA
Zhao, Bingrui
Wang, Yaonan
Zhang, Hui
Zhang, Jinzhou
Chen, Yurong
Yang, Yimin
[J]. IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, 2023, 72 : 1 - 10
[3] Design and Implementation of FPGA Soft Core Processor forLow Power Multicore Embedded Systemusing VHDL
Kinage, Manjusha M.
Khairnar, D. G.
[J]. 2016 INTERNATIONAL CONFERENCE ON AUTOMATIC CONTROL AND DYNAMIC OPTIMIZATION TECHNIQUES (ICACDOT), 2016, : 328 - 332
[4] Design and Implementation of a CMOS 4-Bit 12-GS/s Data Acquisition System-on-Chip
Javid, Behrooz
Heydari, Payam
[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2014, 22 (10) : 2164 - 2175

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