Extreme edge engineering - 2mm Edge exclusion challenges and cost-effective solutions for yield enhancement in high volume manufacturing for 200 and 300mm wafer fabs

被引：6

作者：

Tran, T ^{[1
]}

Roberts, W ^{[1
]}

Tiffany, J ^{[1
]}

Jekauc, I ^{[1
]}

Clements, N ^{[1
]}

Jowett, P ^{[1
]}

Ferguson, R ^{[1
]}

Mattson, D ^{[1
]}

Demmert, C ^{[1
]}

Richmond, M ^{[1
]}

Wiendl, C ^{[1
]}

Bruno, M ^{[1
]}

Brock, A ^{[1
]}

Taylor, T ^{[1
]}

机构：

[1] Infineon Technol, Richmond, VA USA

来源：

2004 IEEE/SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE AND WORKSHOP: ADVANCING THE SCIENCE AND TECHNOLOGY OF SEMICONDUCTOR MANUFACTURING EXCELLENCE | 2004年

关键词：

D O I：

10.1109/ASMC.2004.1309614

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

Signficant financial benefits are realized by reducing the wafer edge exclusion to gain additional productive chips as well as enhance the yield of the former edge-most region of the wafer. Challenges are discussed and cost-effective solutions provided for major unit process and integration issues such as plasma-etch induced blocked/distorted pattern, image displacement, interlayer misalignment, lithography edge coating and patterning, pattern-density-dependent CMP and Etch non-uniformity, scribe readability, and shared-driver shorts.

引用

页码：453 / 460

页数：8