Using formal specifications for functional validation of hardware designs

被引：0
|
作者：
Shimizu, K [1 ]
Dill, DL [1 ]
机构：
[1] Stanford Univ, Comp Syst Lab, Stanford, CA 94305 USA
来源：
IEEE DESIGN & TEST OF COMPUTERS | 2002年 / 19卷 / 04期
关键词：
D O I：
10.1109/MDT.2002.1018138
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Formal specifications can help resolve both ambiguity issues and correctness problems in verifying complex hardware designs. This new methodology shows how specifications can also help design productivity by automating many procedures that are now done manually. Input sequences, output assertions, and a simulation coverage metric for the design under verification are all generated directly from the specification.
引用
收藏
页码：96 / 106
页数：11
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