Thermal management using planarized CVD-diamond substrates

CVD diamond (CVDD) substrates offer an outstanding solution for various advanced electronic packaging applications such as high power 3-D MCMS, laser diodes, and high power MOSFETs. In the manufacturing of such substrates, various post-synthesis processing steps, such as polishing, cutting, and metallization, add significantly to the cost of the package. Recently, we introduced a planarization-by-filling process to reduce the cost of polishing and increase the ease of manufacturing. The process involves surface planarization of coarsely-lapped diamond substrates using a filler material such as polyimide. In the past, we demonstrated successfully the applicability of this planarization process. In this paper, we present results of a parametric thermal management study on such substrates under various ambient conditions. Specifically, the results of experimental work and finite element analysis (FEA) directed at determining maximum die temperature for various power densities using liquid convection for edge cooling are presented. Also, the paper presents results of a thermal stress study, using thermal shock, for GaAs laser diodes mounted, using gold-tin solder, on a diamond substrate planarized using PI-2610 and 2611 polyimides.