Stress Impact of Thermal-Mechanical Loads Measured with the Stress Chip

The experimental observation of the actual thermo mechanical weak points in microelectronics packages remains a big challenge. Recently, a stress sensing system has been developed by a publicly funded project that allows measuring the magnitudes and the distribution of the stresses induced in the silicon dies by thermo-mechanical loads. Some application experiments will be presented, e. g. thermal loads, 4-point bending on CoB setups, and moisture swelling. The stress chip was detecting CTE mismatch, transition temperature, delamination, creep relaxations and volume swelling of moisture loads. All measurements are supplemented by finite element simulations based on calibrated models for in-depth analysis and for extrapolating the stress results to sites of the package that cannot measured directly. The methodology of closely combining stress measurements at inner points and FE simulation presented in this paper has been able to validate the stress sensing system for tasks of comprehensive design and process characterization as well as for health monitoring. It allows achieving both, a substantial reduction in time to- market and a high level of reliability under service conditions, as needed for future electronics and smart systems packages.