Application-oriented fast fault simulator for FPGAs

被引：0
|
作者：
Deniziak, S [1 ]
Sapiecha, K [1 ]
机构：
[1] Krakow Technol Univ, PL-31155 Krakow, Poland
来源：
PROGRAMMABLE DEVICES AND SYSTEMS 2001 | 2002年
关键词：
fault diagnosis; digital systems; simulators; testability; ternary logic;
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper a new efficient approach to bit-parallel fault simulation for FPGA-based sequential systems is introduced and evaluated with the help of ISCAS89 benchmarks. Reduced Ordered Ternary Decision Diagrams (ROTDD) are used to describe functions of LUTs. This lead to substantial reduction of both, the number of simulated faults and calculations needed for simulation. Moreover, an approach presented in this paper is able to handle internal CLB faults in addition to interconnection faults. Copyright (C) 2001 IFAC.
引用
收藏
页码：241 / 246
页数：6
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