A novel processor architecture for real-time control

被引:0
|
作者
Wu, Xiaofeng [1 ]
Chouliaras, Vassilios
Nunez-Yanez, Jose
Goodall, Roger
Vladimirova, Tanya
机构
[1] Univ Surrey, Dept Elect Engn, Surrey Space Ctr, Guildford GU2 7XH, Surrey, England
[2] Univ Loughborough, Dept Elect & Elect Engn, Loughborough LE11 1SN, Leics, England
[3] Univ Bristol, Dept Elect Engn, Bristol BS8 1UB, Avon, England
关键词
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暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper describes a control system processor architecture based on Delta Sigma modulation (Delta Sigma-CSP). The Delta Sigma-CSP uses 1-bit processing which is a new concept in digital control to remove multi-bit multiplications. A simple conditional-negate-and-add (CNA) unit is proposed for most operations of control laws. For this reason, the targeted processor is small and very fast, making it ideal for embedded real-time control applications. The Delta Sigma-CSP has been implemented as a VLSI hard macro in a high-performance 0.13/mu m silicon process. Results show that it compares very favorably to other digital processors in terms of area and clock frequency.
引用
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页码:270 / 280
页数:11
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