FIDP: A novel architecture for lifting-based 2D DWT in JPEG2000

被引:0
|
作者
Li, Bao-Feng [1 ]
Dou, Yong [1 ]
机构
[1] NUDT, Natl Lab Parallel & Distributed Proc, Changsha, Hunan Province, Peoples R China
来源
基金
美国国家科学基金会;
关键词
D O I
暂无
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
In this paper, we propose a deeply parallel architecture called Fragment-based Interleaving Dual Pipelines(FIDP) which can exploit all parallelisms in Lifting-based 2D DWT algorithm. FIDP adopts a fragment-based samples consumption policy and consists of two row processors and two column processors. These processors are organized as interleaving dual pipelines to operate effectively. FIDP takes N-2/4+N/2+1 cycles to finish a N x N 2D DWT while requires only 5N+2 buffer.
引用
收藏
页码:373 / +
页数:2
相关论文
共 50 条
  • [1] High performance architecture for the lifting-based DWT used in JPEG2000
    Zhu, K
    Hua, L
    Zhou, XF
    Zhang, QL
    [J]. 2003 5TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2003, : 946 - 949
  • [2] The lifting-based DWT filter hardware design for JPEG2000
    Yoon, KiTae
    Bae, SeungSoo
    Choi, ShinHyuk
    Choi, JunRim
    [J]. ISOCC: 2008 INTERNATIONAL SOC DESIGN CONFERENCE, VOLS 1-3, 2008, : 160 - 163
  • [3] A novel architecture for lifting-based discrete wavelet transform for JPEG2000 standard suitable for VLSI implementation
    Movva, S
    Srinivasan, S
    [J]. 16TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 2003, : 202 - 207
  • [4] Novel VLSI architecture of 2-D DWT/IDWT for JPEG2000 based on diagonal storage
    Qin, X
    Yan, XL
    Yang, CP
    Zhao, X
    [J]. 2004: 7TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUITS TECHNOLOGY, VOLS 1- 3, PROCEEDINGS, 2004, : 1657 - 1660
  • [5] VLSI architecture of DWT for JPEG2000
    Liu, Lei-Bo
    Wang, Xue-Jin
    Meng, Hong-Ying
    Wang, Zhi-Hua
    Chen, Hong-Yi
    Xia, Yu-Wen
    [J]. Tien Tzu Hsueh Pao/Acta Electronica Sinica, 2002, 30 (11): : 1609 - 1612
  • [6] Novel Memory Efficient Hardware Architecture for 5/3 Lifting-Based 2D Inverse DWT
    Savic, Goran
    Rajovic, Vladimir
    [J]. JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2019, 28 (07)
  • [7] VLSI architecture of low memory and high speed 2-D lifting-based discrete wavelet transform for JPEG2000 applications
    Chiang, JS
    Hsia, CH
    Chen, HJ
    Lo, TJ
    [J]. 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 4554 - 4557
  • [8] A Reconfigurable Architecture for DWT and IDWT in JPEG2000
    Hong Qi
    Wang Kanwen
    Cao Wei
    Tong Jiarong
    [J]. 2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2009, : 191 - 194
  • [9] On a novel dynamic parallel hardware architecture for lifting-based DWT
    Khanfir, Sami
    Jemni, Mohamed
    [J]. EURO-PAR 2008 PARALLEL PROCESSING, PROCEEDINGS, 2008, 5168 : 846 - 855
  • [10] A new VLSI architecture of lifting-based DWT
    Seo, Young-Ho
    Kim, Dong-Wook
    [J]. RECONFIGURABLE COMPUTING: ARCHITECTURES AND APPLICATIONS, 2006, 3985 : 146 - 151