A 1,000 Frames/s Programmable Vision Chip with Variable Resolution and Row-Pixel-Mixed Parallel Image Processors

被引:16
|
作者
Lin, Qingyu [1 ]
Miao, Wei [1 ]
Zhang, Wancheng [1 ]
Fu, Qiuyu [1 ]
Wu, Nanjian [1 ]
机构
[1] Chinese Acad Sci, Inst Semicond, State Key Lab Superlattices & Microstruct, Beijing 100083, Peoples R China
关键词
vision chip; image processing; machine vision; mathematical morphology; HIGH-SPEED; LEVEL ADC; SENSOR; DESIGN;
D O I
10.3390/s90805933
中图分类号
O65 [分析化学];
学科分类号
070302 ; 081704 ;
摘要
A programmable vision chip with variable resolution and row-pixel-mixed parallel image processors is presented. The chip consists of a CMOS sensor array, with row-parallel 6-bit Algorithmic ADCs, row-parallel gray-scale image processors, pixel-parallel SIMD Processing Element (PE) array, and instruction controller. The resolution of the image in the chip is variable: high resolution for a focused area and low resolution for general view. It implements gray-scale and binary mathematical morphology algorithms in series to carry out low-level and mid-level image processing and sends out features of the image for various applications. It can perform image processing at over 1,000 frames/s (fps). A prototype chip with 64 x 64 pixels resolution and 6-bit gray-scale image is fabricated in 0.18 mu m Standard CMOS process. The area size of chip is 1.5 mm x 3.5 mm. Each pixel size is 9.5 mu m x 9.5 mu m and each processing element size is 23 mu m x 29 mu m. The experiment results demonstrate that the chip can perform low-level and mid-level image processing and it can be applied in the real-time vision applications, such as high speed target tracking.
引用
收藏
页码:5933 / 5951
页数:19
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