Two-step split-junction SAR ADC

被引:5
|
作者
Yu, W. [1 ]
Lin, J. [1 ]
Temes, G. C. [1 ]
机构
[1] Oregon State Univ, Sch Elect Engn & Comp Sci, Corvallis, OR 97331 USA
关键词
D O I
10.1049/el.2010.2392
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A new architecture is proposed to reduce the power consumption and capacitor area in successive-approximation register analogue-to-digital converters (SAR ADCs). Two split-junction binary-weighted capacitor arrays are used in a coarse/fine quantisation scheme. This reduces both the power consumption and the capacitor area to a small fraction of that of the original split-junction SAR ADC.
引用
收藏
页码:208 / 209
页数:2
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