VLSI compressor design with applications to digital neural networks

A key problem for implementing high-performance, high-capacity digital neural networks (DNN) is to design effective VLSI compressors to reduce the impact of carry propagation of large data matrix. Tn this paper, such a compressor design based on complex complementary pass-transistor logic ((CPL)-P-2) is presented. Some types of 3-2 compressors in (CPL)-P-2 are implemented and a number of experiments are conducted to optimize their performance. Two typical building blocks, 4-2 and 7-3 compressors, are developed and their DNN applications are discussed. Compared with the complementary pass-transistor logic (CPL) and the conventional direct logic (CDL), our simulations show that the (CPL)-P-2 compressors have the best performance in power, delay and number of transistors.