Self-aligned gates for scalable silicon quantum computing

被引:26
|
作者
Geyer, Simon [1 ]
Camenzind, Leon C. [1 ]
Czornomaz, Lukas [2 ]
Deshpande, Veeresh [2 ,3 ]
Fuhrer, Andreas [2 ]
Warburton, Richard J. [1 ]
Zumbuhl, Dominik M. [1 ]
Kuhlmann, Andreas V. [1 ,2 ]
机构
[1] Univ Basel, Dept Phys, Klingelbergstr 82, CH-4056 Basel, Switzerland
[2] IBM Res Zurich, Saumerstr 4, CH-8803 Ruschlikon, Switzerland
[3] Helmholtz Zentrum Berlin Mat & Energie, Inst IFOX, Hahn Meitner Pl 1, D-14109 Berlin, Germany
基金
欧盟地平线“2020”;
关键词
All Open Access; Green;
D O I
10.1063/5.0036520
中图分类号
O59 [应用物理学];
学科分类号
摘要
Silicon quantum dot spin qubits have great potential for application in large-scale quantum circuits as they share many similarities with conventional transistors that represent the prototypical example for scalable electronic platforms. However, for quantum dot formation and control, additional gates are required, which add to device complexity and, thus, hinder upscaling. Here, we meet this challenge by demonstrating the scalable integration of a multilayer gate stack in silicon quantum dot devices using self-alignment, which allows for ultrasmall gate lengths and intrinsically perfect layer-to-layer alignment. We explore the prospects of these devices as hosts for hole spin qubits that benefit from electrically driven spin control via spin-orbit interaction. Therefore, we study hole transport through a double quantum dot and observe current rectification due to the Pauli spin blockade. The application of a small magnetic field leads to lifting of the spin blockade and reveals the presence of spin-orbit interaction. From the magnitude of a singlet-triplet anticrossing at a high magnetic field, we estimate a spin orbit energy of similar to 37 mu eV, which corresponds to a spin orbit length of similar to 48nm. This work paves the way for scalable spin- based quantum circuits with fast, all-electrical qubit control. Published under license by AIP Publishing.
引用
收藏
页数:6
相关论文
共 50 条
  • [1] Scalable fabrication of high performance graphene FETs with self-aligned buried gates
    Wang, Yanjie
    Huang, Bo-Chao
    Zhang, Ming
    Miao, Congqin
    Xie, Ya-Hong
    Woo, Jason C. S.
    [J]. 2012 IEEE 11TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT-2012), 2012, : 347 - 350
  • [2] Self-aligned silicon quantum wires on Ag(110)
    Leandri, C
    Le Lay, G
    Aufray, B
    Girardeaux, C
    Avila, J
    Dávila, ME
    Asensio, MC
    Ottaviani, C
    Cricenti, A
    [J]. SURFACE SCIENCE, 2005, 574 (01) : L9 - L15
  • [3] Nanoscale silicon field emitter arrays with self-aligned extractor and focus gates
    Rughoobur, Girish
    Karaulac, Nedeljko
    Jain, Lay
    Omotunde, Olutimilehin O.
    Akinwande, Akintunde, I
    [J]. NANOTECHNOLOGY, 2020, 31 (33)
  • [4] Technique for fabricating self-aligned gates onto silicon field emitter arrays
    Zhu, CC
    Guan, H
    Liu, WD
    Li, TY
    Sin, JKO
    [J]. JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 1997, 15 (05): : 1682 - 1684
  • [5] Graphene-Based Quantum Hall Interferometer with Self-Aligned Side Gates
    Zhao, Lingfei
    Arnault, Ethan G.
    Larson, Trevyn F. Q. .
    Iftikhar, Zubair
    Seredinski, Andrew
    Fleming, Tate
    Watanabe, Kenji
    Taniguchi, Takashi
    Amet, Francois
    Finkelstein, Gleb
    [J]. NANO LETTERS, 2022, 22 (23) : 9645 - 9651
  • [6] A self-aligned fabrication process for silicon quantum computer devices
    Buehler, TM
    McKinnon, RP
    Lumpkin, NE
    Brenner, R
    Reilly, DJ
    Macks, LD
    Hamilton, AR
    Dzurak, AS
    Clark, RG
    [J]. NANOTECHNOLOGY, 2002, 13 (05) : 686 - 690
  • [7] Nanofabrication of arrays of silicon field emitters with vertical silicon nanowire current limiters and self-aligned gates
    Guerrera, S. A.
    Akinwande, A. I.
    [J]. NANOTECHNOLOGY, 2016, 27 (29)
  • [8] Fabrication of self-aligned side gates to carbon nanotubes
    Robinson, LAW
    Lee, SB
    Teo, KBK
    Chhowalla, M
    Amaratunga, GAJ
    Milne, WI
    Williams, DA
    Hasko, DG
    Ahmed, H
    [J]. NANOTECHNOLOGY, 2003, 14 (02) : 290 - 293
  • [9] METAL-NITRIDE-OXIDE-SILICON FIELD-EFFECT TRANSISTORS WITH SELF-ALIGNED GATES
    SARACE, JC
    KERWIN, RE
    KLEIN, DL
    EDWARDS, R
    [J]. SOLID-STATE ELECTRONICS, 1968, 11 (07) : 653 - +
  • [10] Robust, scalable self-aligned platinum silicide process
    Zhang, Z
    Zhang, SL
    Östling, M
    Lu, J
    [J]. APPLIED PHYSICS LETTERS, 2006, 88 (14)