Massively Parallel Tree Search for High-Dimensional Sphere Decoders

被引:20
|
作者
Nikitopoulos, Konstantinos [1 ]
Georgis, Georgios [1 ]
Jayawardena, Chathura [1 ]
Chatzipanagiotis, Daniil [1 ]
Tafazolli, Rahim [1 ]
机构
[1] Univ Surrey, ICS, 5G Innovat Ctr, Guildford GU2 7XH, Surrey, England
基金
英国工程与自然科学研究理事会;
关键词
Sphere decoding; parallel processing; large multiple-input-multiple-output (MIMO); lattice search; HIGH-THROUGHPUT; REDUCTION CIRCUITS; MIMO; IMPLEMENTATION; ALGORITHM; DESIGN; COMPLEXITY;
D O I
10.1109/TPDS.2018.2874002
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
The recent paradigm shift towards the transmission of large numbers of mutually interfering information streams, as in the case of aggressive spatial multiplexing, combined with requirements towards very low processing latency despite the frequency plateauing of traditional processors, initiates a need to revisit the fundamental maximum-likelihood (ML) and, consequently, the spheredecoding (SD) detection problem. This work presents the design and VLSI architecture of MultiSphere; the first method to massively parallelize the tree search of large sphere decoders in a nearly-concurrent manner, without compromising their maximum-likelihood performance, and by keeping the overall processing complexity comparable to that of highly-optimized sequential sphere decoders. For a 10 x 10 MIMO spatially multiplexed system with 16-QAM modulation and 32 processing elements, our MultiSphere architecture can reduce latency by 29 x against well-known sequential SDs, approaching the processing latency of linear detection methods, without compromising ML optimality. In MIMO multicarrier systems targeting exact ML decoding, MultiSphere achieves processing latency and hardware efficiency that are orders of magnitude improved compared to approaches employing one SD per subcarrier. In addition, for 16 x 16 both "hard"-and "soft"-output MIMO systems, approximate MultiSphere versions are shown to achieve similar error rate performance with state-of-the art approximate SDs having akin parallelization properties, by using only one tenth of the processing elements, and to achieve up to approximately 9x increased energy efficiency.
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页码:2309 / 2325
页数:17
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