Static power modeling of 32-bit microprocessors

被引：14

作者：

Brandolese, C ^{[1
]}

Salice, F ^{[1
]}

Fornaciari, W ^{[1
]}

Sciuto, D ^{[1
]}

机构：

[1] Politecn Milan, Dipartimento Elettron & Informat, I-20133 Milan, Italy

来源：

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 2002年 / 21卷 / 11期

关键词：

embedded systems; estimation; low-power design; modeling; power modeling and estimation;

D O I：

10.1109/TCAD.2002.804104

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The paper presents a novel strategy aimed at modeling instruction energy consumption of 32-bit microprocessors. Different from former approaches, the proposed instruction-level power model is founded on a functional decomposition of the activities accomplished by a generic microprocessor. The proposed model has significant generalization capabilities. It allows estimation of the power figures of the entire instruction-set starting from the analysis of a subset, as well as to power characterize new processors by using the model obtained by considering other microprocessors. The model is formally presented and justified and its actual application over five commercial microprocessors is included. This static characterization is the basic information for system-level power modeling of hardware/software architectures.

引用

页码：1306 / 1316

页数：11

共 50 条

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