Decoding Algorithm for Quadruple-Error-Correcting Reed-Solomon Codes and Its Derived Architectures

被引:1
|
作者
Garcia-Herrero, Francisco [1 ]
McGuire, Gary [2 ]
Flanagan, Mark F. [2 ]
Sanchez-Macian, Alfonso [1 ]
Maestro, Juan Antonio [1 ]
机构
[1] Univ Nebrija, ARIES Res Ctr, Madrid 28015, Spain
[2] Univ Coll Dublin, Sch Elect Elect & Commun Engn, Dublin D04 V1W8 4, Ireland
关键词
Decoding; Computer architecture; Hardware; Mathematical model; Circuits and systems; Reed-Solomon codes; Proposals; Error correction; memory protection;
D O I
10.1109/TCSII.2020.3038462
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This brief introduces a new method to compute in parallel the roots of a polynomial locator of degree four in a Reed-Solomon decoder. The novelty of this brief is the introduction of an algorithm that transforms the polynomial locator obtained with the Peterson-Gorenstein-Zierler's algorithm into an equivalent one that allows a direct search for the four roots that indicate the location of the symbols in error. This new solution improves a previous approach proposed in the literature for a quadruple-error-correction decoder (QEC) that requires a cubic aid equation. This previous solution does not work in the cases in which the cubic aid does not have a solution. In contrast, the proposal of this brief works in 100% of cases (with t <= 4) as it solves an equivalent polynomial. This new algorithm allows two different implementations: a fully parallel architecture which provides an extremely low latency at an extra area cost, and a fully serial architecture with less area, but a higher latency.
引用
收藏
页码:1438 / 1442
页数:5
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