Novel Ultra Low Leakage FinFET Based SRAM Cell

To make portable battery operated devices more efficient with low leakage current is a major challenge with the technology scaling. The power dissipation is expected to increase further in next generation technologies because of the exponential increase in leakage currents with technology scaling. FinFET device was introduced as a suitable replacement of CMOS due to its reduced short channel effects at lower technology nodes. However, leakage current still remains comparable to device ON current at highly scaled technology nodes. Continuous voltage supply to retain the data in SRAM cell contributes a major part of leakage current in any processor design. This paper proposed a novel circuit technique to reduce the leakage current and power consumption of SRAM cell. The proposed design achieves a very high reduction in static power dissipation, up to 4% reduction in read power and upto 49% reduction in write power dissipation as compared to conventional FinFET 6T SRAM cell. All the HPSICE simulation is performed using 32nm BSIM technology file.