Neural Networks and FPGA Hardware Accelerators for Millimeter-Wave Radio-over-Fiber Systems

被引:10
|
作者
Lee, Jeonghun [1 ]
He, Jiayuan [2 ]
Wang, Ke [1 ]
机构
[1] Royal Melbourne Inst Technol RMIT Univ, Sch Engn, Melbourne, Vic 3000, Australia
[2] Univ Melbourne, Sch Comp & Informat Syst, Melbourne, Vic 3010, Australia
关键词
millimeter-wave radio-over-fiber system; convolutional neural network; binary convolutional neural network; field programmable gate array; neural network hardware accelerator;
D O I
10.1109/icton51198.2020.9203559
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
High speed data streaming has been highly demanded by mobile end users and millimetre-wave (mm-wave) radio-over-fiber (RoF) optical communications have been studied to satisfy the users' demands. To solve various impairments existing in mm-wave RoF systems, neural networks have been proposed and studied due to their capability in solving nonlinear effects and multiple impairments simultaneously. However, previous studies mainly focused on the fully-connected neural network (FC-NN), which has relatively complicated architecture and a large number of parameters to be learnt. To solve this issue, we have proposed the convolutional neural network (CNN) and binary convolutional neural network (BCNN) based decision schemes. In addition, the neural networks in previous studies are typically implemented offline using high-end CPUs or GPUs, which are not practical for optical communication applications. To solve this issue, we have proposed the field-programmable gate array (FPGA) based hardware accelerators, which have the key advantages of reconfigurability, low power consumption, and parallel computation capability. A novel inner parallel optimization method has also proposed to improve the latency with minimal additional power consumption. Results show that the CNN/BCNN implemented with GPU and with the FPGA-based hardware accelerator achieves similar BER performance within the forward-error-correction (FEC) limit, while the FPGA-based hardware accelerators reduce the power consumption significantly.
引用
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页数:4
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