A floating-point processor for fast and accurate sine/cosine evaluation

A VLSI architecture for fast and accurate floating-point sine/cosine evaluation is presented, combining floating-point and simple fixed-point arithmetic. The algorithm implemented by the architecture is based on second-order polynomial interpolation within an approximation interval which is partitioned into regions of unequal length. The exploitation of certain properties of the trigonometric functions and of specific bit patterns that appear in the involved computations, has led to reduced memory size and low overall hardware complexity. In fact, a 40% memory size reduction is achieved by the introduced simplified memory interleaving scheme, when compared to a traditional interleaved memory architecture. The proposed architecture has been designed and simulated in a 0.7-mu m CMOS process technology, to prove its amenability for VLSI implementation, The time required to evaluate a sine is less than the time required for three single-precision floating-point multiply-accumulate (MAC) operations, while the computed values are guaranteed to be accurate to half a unit in last position (ulp), To prove the accuracy of the algorithm, an error analysis for the computation of second-order Horner polynomial is provided, based on novel formulae which have been recently introduced in the literature by the authors for roundoff error bounds in floating-point addition and multiplication.