The Collaborative Design for the Package of High - speed Interface Chip

被引：0
|
作者：
Bai, Lijuan [1 ]
He, Huimin [2 ]
Liu, Fengman [2 ]
Li, Jun [2 ]
Cao, Liqiang [2 ]
机构：
[1] Univ Sci & Technol China, Sch Microelect, Chinese Acad Sci, Microsyst Packaging Res Ctr,Inst Microelect, Beijing, Peoples R China
[2] Chinese Acad Sci, Inst Microelect, Microsyst Packaging Res Ctr, Beijing, Peoples R China
来源：
2020 21ST INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY (ICEPT) | 2020年
关键词：
Collaborative design; DDR3; Signal integrity; Power integrity;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In order to meet people's demand for multi-function and miniaturization of electronic products, the integration degree of electronic products is constantly improving and the speed is getting faster and faster. The research takes an actual DDR3 controller package design as the background. And the chip adopts advanced packaging collaborative design, including die-package-PCB collaboration design and design-simulation collaboration design. Packaging is evaluated in terms of electrical integrity, thermal mechanical properties, manufacturability, testability and so on during package.
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页数：4
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