A Self-partial Reconfiguration Framework with Configuration Data Compression for Intel FPGAs

被引：0

作者：

Fukui, Shota ^{[1
]}

Kawamata, Yuichi ^{[1
]}

Shibata, Yuichiro ^{[1
]}

机构：

[1] Nagasaki Univ, Grad Sch Engn, 1-14 Bunkyo Machi, Nagasaki 8528521, Japan

来源：

COMPLEX, INTELLIGENT, AND SOFTWARE INTENSIVE SYSTEMS (CISIS 2019) | 2020年 / 993卷

关键词：

D O I：

10.1007/978-3-030-22354-0_39

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

In this paper, we implement and evaluate a self-partial reconfiguration (Self-PR) system, where configuration data for partial reconfiguration (PR) is stored in the hard macro memory on FPGA, and PR is performed from the inside of FPGA. As a result, in the case of the smallest PR region, the time required for Self-PR is about 2.8ms, 97% less than using JTAG interface. The usage of hard macro memory blocks is about 21% of the total resources. We additionally implement and evaluate a mechanism that compresses the configuration data for PR, and the module that decompresses the data in the FPGA. As a result, the usage of hard macro memory blocks was reduced to 3% of the total resources. The increase in resource usage and the decrease in FMax due to addition of decompress circuit were quite limited, and there was no additional latency. Therefore, Self-PR with compressed configuration data can be performed in the same speed as when the compression mechanism was not utilized.

引用

页码：442 / 452

页数：11

共 8 条

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