Requirements for time-to-digital converters in the context of digital-PLL based frequency synthesis and GSM modulation

被引：9

作者：

Vollenbruch, Ulrich ^{[1
]}

Liu, Yue ^{[2
]}

Bauernfeind, Thomas ^{[2
]}

Pittorino, Tindaro ^{[2
]}

Neubauer, Volker ^{[3
]}

Mayer, Thomas ^{[3
]}

Maurer, Linus ^{[3
]}

机构：

[1] Linz Ctr Mechatron GmbH, Altenbergerstr 69, A-4040 Linz, Austria

[2] Univ Linz, Res Inst Integrated Circuits, A-4040 Linz, Austria

[3] DICE GmbH, Co KG, A-4040 Linz, Austria

来源：

2006 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST, VOLS 1-5 | 2006年

关键词：

frequency synthesizers; GSM; phase locked loops; phase detector; Sigma Delta-modulation; digital PLL; Time-to-Digital converter;

D O I：

10.1109/MWSYM.2006.249748

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A key issue in proceeding the digitization of Phase-Locked Loops (PLLs) is the realization of proper phase detectors in the digital domain. This paper presents simulative analysis of the properties and requirements for Time-to-Digital Converters (TDCs) used for phase comparison in digitized fractional-N modulators with two-point modulation. Effects due to quantization of the TDC on frequency synthesis as well as GSM modulation quality are considered, defining the realization requirements for a transmitter.

引用

页码：1817 / +

页数：2

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