An efficient line-based architecture using lifting scheme and its VLSI implementation for 2D wavelet transform

In this paper, an efficient architecture for the lifting based two dimensional wavelet transform is presented. Proposed modular architecture with regular data flow is a hybrid of standard level by level and line based architectures. It reduces the internal memory requirement and introduces the advantage of integer lifting. Both the left and right boundaries have been treated well without spending any extra clock cycle and keeping boundary information properly. When the pipelined structure of the column processor and row processor are filled by data, for every clock cycle these two processors as well as the internal memory are busy. So, 100% hardware utilization is achieved. For real time processing, the proposed architecture has been implemented through proper pipelining and parallelism targeting VIRTEX 1000bg-560 FPGA to achieve high throughput of 63 MHz with reasonable latency.