Design and implementation of ATM NIC in FPGA

Man's thirst for processor speed resulted in high performance processors. In order to exploit the performance need was felt for high-speed bus architecture. One such high-speed bus architecture is the Peripheral Component Interconnect (PCI). The PCI bus can be populated with adapters requiring fast accesses to each other and/or system memory and that can be accessed by the processor at speeds approaching that of the processor's full native bus speed. One of the highly used adapters is the Network Interface Card (NIC). This paper is about the design and implementation of ATM NIC using FOGA technology. The ATM NIC includes a PCI master interface for the host system's PCI bus. This interface provides efficient, low latency transfers to and from the host memory. Further, the master transfer method of NIC relieves the host system processor from most of the activities involved in ATM communication. The device driver only needs to write and maintain small descriptors in the host memory and to update pointers in local memory for the NIC. All ATM cell payload as well as all key descriptor transfers, are controlled by the NIC. This ATM NIC design is capable of implementing segmentation and reassembly functions for AAL 5 communications, including the control and interface to the ATM physical layer interface. The verification of the design has been done with the aid of a test-bench. The PCI Interface is a 32-bit version and is modeled with Verilog HDL. The details of the design specifications, constraints, tradeoffs, device utilization and power consumption have been reported.