A low power SRAM cell design for wireless sensor network applications

被引：6
|
作者：
Pal, Soumitra [1 ]
Bose, Subhankar [2 ]
Islam, Aminul [2 ]
机构：
[1] Hong Kong Univ Sci & Technol, Dept Elect & Comp Engn, Clear Water Bay, Hong Kong, Peoples R China
[2] Birla Inst Technol, Dept Elect & Commun Engn, Ranchi 835215, Jharkhand, India
来源：
MICROSYSTEM TECHNOLOGIES-MICRO-AND NANOSYSTEMS-INFORMATION STORAGE AND PROCESSING SYSTEMS | 2020年 / 26卷 / 07期
关键词：
BIT-LINE; SUBTHRESHOLD SRAM; 8T SRAM; 9T SRAM; WRITE; CMOS;
D O I：
10.1007/s00542-019-04708-5
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A Fully Differential Write Assist 10T (FDWA10T) SRAM cell has been proposed in this work. The various design metrics and their behavior under severe process variation have been analyzed in this paper and have been compared with other state-of-the-art designs - FD8T, SEDF9T, BI11T, WWL12T and D12T cells. The FDWA10T cell shows 1.47x/1.73x/2.09x shorter TRA than that of D12T/BI11T/SEDF9T and 1.20x/1.59x/1.86x/4.33x shorter TWA than that of D12T/WWL12T/SEDF9T/BI11T. In addition, it shows 1.05x narrower spread in TRAthan that of BI11T and 3.94 higher RSNM than that of FD8T. A 4.10x improvement in WSNM is also observed when compared to SEDF9T/D12T/WWL12T. The FDWA10T cell also exhibits 1.03x/1.03x/1.06x/2.09x lower hold power (HPWR consumption than that of D12T/FD8T/SEDF9T/WWL12T and consumes 1.14x/1.26x/1.23 lesser area when compared to BI11T/WWL12T/D12T. These improvements are obtained at the cost of 1.50x/2.42x longer TRA/TWA than that of FD8T, 6.4x$$6.4\times$$\end{document} higher HPWR dissipation than that of BI11T and 1.10x/1.15x higher area consumption than that of FD8T/SEDF9T.
引用
收藏
页码：2325 / 2335
页数：11
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