Remote path delay fault simulation

被引：0
|
作者：
Gjermundnes, O [1 ]
Aas, EJ [1 ]
机构：
[1] NTNU, Dept Elect & Telcommun, N-7491 Trondheim, Norway
来源：
DSD 2005: 8TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN, PROCEEDINGS | 2005年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper describes the design of a remote fault simulator for delay faults that can be used by students to investigate the effect of different stimuli generators for different types of delay fault models.
引用
收藏
页码：428 / 434
页数：7
相关论文
共 50 条
  • [1] Path delay fault simulation of sequential circuits
    Chakraborty, TJ
    Agrawal, VD
    Bushnell, ML
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2000, 8 (02) : 223 - 228
  • [2] On the nonenumerative path delay fault simulation problem
    Kagaris, D
    Tragoudas, S
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2002, 21 (09) : 1095 - 1101
  • [3] PARALLEL PATTERN FAULT SIMULATION OF PATH DELAY FAULTS
    SCHULZ, MH
    FINK, F
    FUCHS, K
    [J]. 26TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, 1989, : 357 - 363
  • [4] Path delay fault simulation on large industrial designs
    Naturajan, Suriyaprakash
    Patil, Srinivas
    Chakravarty, Sreejit
    [J]. 24TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2006, : 16 - +
  • [5] The path-status graph with application to delay fault simulation
    Gharaybeh, MA
    Bushnell, ML
    Agrawal, VD
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1998, 17 (04) : 324 - 332
  • [6] False-Path Removal Using Delay Fault Simulation
    Marwan A. Gharaybeh
    Vishwani D. Agrawal
    Michael L. Bushnell
    Carlos G. Parodi
    [J]. Journal of Electronic Testing, 2000, 16 : 463 - 476
  • [7] On Accelerating Path Delay Fault Simulation of Long Test Sequences
    Huang, I-De
    Chang, Yi-Shing
    Natarajan, Suriyaprakash
    Sharma, Ramesh
    Gupta, Sandeep K.
    [J]. 2008 IEEE INTERNATIONAL TEST CONFERENCE, VOLS 1 AND 2, PROCEEDINGS, 2008, : 710 - +
  • [8] False-path removal using delay fault simulation
    Gharaybeh, MA
    Agrawal, VD
    Bushnell, ML
    Parodi, CG
    [J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2000, 16 (05): : 463 - 476
  • [9] False-path removal using delay fault simulation
    Gharaybeh, MA
    Agrawal, VD
    Bushnell, ML
    [J]. SEVENTH ASIAN TEST SYMPOSIUM (ATS'98), PROCEEDINGS, 1998, : 82 - 87
  • [10] Efficient path-delay fault simulation for standard scan design
    Kang, S
    [J]. IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 2002, 149 (5-6): : 315 - 320
12345