All Operation Region Characterization and Modeling of Drain and Gate Current Mismatch in 14-nm Fully Depleted SOI MOSFETs

被引：21

作者：

Karatsori, Theano A. ^{[1
,2
]}

Theodorou, Christoforos G. ^{[1
]}

Josse, Emmanuel ^{[3
]}

Dimitriadis, Charalabos A. ^{[2
]}

Ghibaudo, G. ^{[1
]}

机构：

[1] Minatec, Inst Microelect, Electromagnetisme & Photon Lab, Hyperfrequences & Caracterizat Lab, F-38016 Grenoble, France

[2] Aristotle Univ Thessaloniki, Dept Phys, Thessaloniki 54124, Greece

[3] ST Microelect, F-38921 Crolles, France

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2017年 / 64卷 / 05期

关键词：

Electrical characterization; fully depleted silicon-on-insulator (FD-SOI) MOSFETs; mismatch modeling; COMPACT MODEL; VARIABILITY;

D O I：

10.1109/TED.2017.2686381

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we present a complete study of the drain and gate current local variability in high-k/metal gate-stack 14-nm fully depleted silicon-on-insulator CMOS transistors. A thorough experimental characterization of both drain and gate current mismatch was performed. In addition, we developed, for the first time, models of the drain and gate current mismatch, valid in all operation regions. Finally, we demonstrate the universal validity of our models through Monte Carlo simulations.

引用

页码：2080 / 2085

页数：6

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