LRU-MRU With Physical Address Cache Replacement Algorithm On FPGA Application

A caching model is proposed to accelerate the I/O speed between disks and FPGA devices in the conditions of reconfigurable computing. Especially the speed of FPGA processing is much larger than the RAID reading rate. The accelerating strategy is based on LRU-MRU replacement, adding physical address factors at the same time. In the case of two-cache application mode, the accelerating strategy, according to the characteristics of FPGA application, can accelerate 5% comparing with the traditional LRU-MRU algorithm. Through the quantitative analysis of this algorithm, we propose the cache optimization model of small file to improve disk read rate for FPGA computation.