Impacts of Ti Content and Annealing Temperature on Electrical Properties of Si MOS Capacitors with HfTiON Gate Dielectric

HfTiON gate dielectric is fabricated by reactive co-sputtering method followed by annealing in N-2 ambient. The effects of Ti content and annealing temperature on the performances of HfTiON gate-dielectric Si MOS devices are investigated. Experimental results indicate that gate capacitance is increased with increasing Ti content. However, when the Ti/Hf ratio exceeds similar to 1.75, increase of the gate capacitance becomes small. Surface roughness of the samples annealed at different temperatures is analyzed by AFM, and results show that high annealing temperature (e.g. 700 degrees C for 30 s) can produce smooth surface, thus resulting in low gate leakage current.