Random Number Generation Using Dual Oscillator Architecture and Discrete-Time Chaos

This paper introduces a novel random number generator which is based on Bernoulli discrete-time chaotic map. In order to boost the throughput and to increase the statistical quality of the output sequence, presented RNG is designed using the discrete-time chaotic map together with the dual oscillator architecture. An arithmetic model of the suggested design had been elaborated and it has been algebraically confirmed that the generated bit stream has successfully passed all four primary tests of the FIPS-140-2 test suite. Lastly, it has also been confirmed that the bit stream, which was obtained from the hardware realization of the circuit in a similar way, has passed all the NIST-800-22 tests without any post-processing. The results obtained from the experiment and simulation, which confirm the usefulness of the circuit, are presented. We can build the suggested RNG using the integrated circuit.