A design of HEMT comparators for ultrahigh-speed A/D conversion

被引:2
|
作者
Watanabe, Hiroshi [1 ]
Nakamura, Shunsuke [1 ]
Waho, Takao [1 ]
机构
[1] Sophia Univ, Dept Elect & Elect Engn, Tokyo 1028554, Japan
来源
IEICE TRANSACTIONS ON ELECTRONICS | 2008年 / E91C卷 / 05期
关键词
comparator; D-latch; HEMT; analog-to-digital converter;
D O I
10.1093/ietele/e91-c.5.688
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
HEMT comparators for ultrahigh-speed A/D converters have been investigated. In particular, the transition times of the D-latch used in the comparator have been analyzed by assuming a 0.1-mu m HEMT technology. It is found that for small input signals (< 0.1 V), the transition time from the track to latch phase dominates the comparator operation speed. As the input signal increases, this time decreases due to the positive feedback in the latch, and the comparator speed is limited by the transition time from the latch to track phase. The transition times of 20 ps have been estimated for the present comparator.
引用
收藏
页码:688 / 692
页数:5
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