High Speed Interconnect Optimization

被引：0

作者：

Vasa, Mallikarjun ^{[1
]}

Reddy, Arun Chada ^{[2
]}

Mutnury, Bhyrav ^{[2
]}

Kumar, Sanjay ^{[1
]}

Vasanth, R. D. ^{[3
]}

机构：

[1] Dell Enterprise Server Grp, Bangalore, Karnataka, India

[2] Dell Enterprise Server Grp, Round Rock, TX USA

[3] Ansys, Bangalore, Karnataka, India

来源：

2015 ASIA-PACIFIC INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (APEMC) | 2015年

关键词：

PCB; Interconnect; Voids; Anti-Pads;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

As the signal speeds begin to increase, small routing imperfections start to dictate the overall channel performance. Commonly found routing imperfections such as trace breakout, via discontinuity and AC coupling capacitor pad capacitance need to be further optimized to meet the desired channel specification based on bit error rate (BER). Upfront modeling and analysis of such imperfections at high frequencies can mitigate expensive board redesigns to achieve the desired performance. This paper demonstrates the impact of each such routing imperfection(s) for data rates up to 40 Gbps. Model to hardware correlation is performed to ensure model accuracy. The impact physical routing parameters on return and insertion loss in frequency and time domain are studied to help designers optimize their channel.

引用

页码：8 / 11

页数：4

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