A hierarchical architecture for time- and event-triggered real-time systems

被引:2
|
作者
Real, Jorge [1 ]
Saez, Sergio [2 ]
Crespo, Alfons [1 ]
机构
[1] Univ Politecn Valencia, Inst Automat & Informat Ind, Cami de Vera S-N, E-46022 Valencia, Spain
[2] Univ Politecn Valencia, Inst Tecnol Informat, Cami de Vera S-N, E-46022 Valencia, Spain
关键词
Real-time systems; Time-triggered scheduling; Ravenscar tasking profile; High-integrity systems; Embedded systems;
D O I
10.1016/j.sysarc.2019.101652
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper proposes an architecture for combining the execution of time- and event-triggered real-time task sets. This makes it possible for the designer to choose the most appropriate mechanism depending on the role and nature of each task in the system. The proposed architecture allows one to choose the priority levels at which time- and event-triggered tasks are executed. This gives the designer an additional degree of freedom to make compromise decisions upon contradicting timing requirements, such as granting reduced jitter and at the same time providing prompt service to non-periodic events, for example. The proposed model is accompanied with a Ravenscar implementation of the time-triggered scheduler and a library of utilities for specifying time-triggered schedules and reusing time-triggered task patterns.
引用
收藏
页数:15
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