VLSI layouts of complete graphs and star graphs

被引：10

作者：

Yeh, CH ^{[1
]}

Parhami, B ^{[1
]}

机构：

[1] Univ Calif Santa Barbara, Dept Elect & Comp Engn, Santa Barbara, CA 93106 USA

来源：

INFORMATION PROCESSING LETTERS | 1998年 / 68卷 / 01期

关键词：

complete graphs; star graphs; VLSI layout; parallel processing;

D O I：

10.1016/S0020-0190(98)00133-1

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we present efficient layouts for complete graphs and star graphs. We show that an N-node complete graph can be optimally laid out using [N-2/4] tracks for a colinear layout, and can be laid out in N-4/16 + o(N-4) area for a 2D layout. We also show that an N-node star graph can be laid out in N-2/16 + o(N-2) area, which is smaller than any possible layout of a similar-size hypercube. This solves an open question posed by Akers and Krishnamurthy in 1986. Both the layouts of complete graphs and star graphs are optimal within a factor 1 + o(1). (C) 1998 Published by Elsevier Science B.V. All rights reserved.

引用

页码：39 / 45

页数：7

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