Formal Verification of Fault-Tolerant and Recovery Mechanisms for Safe Node Sequence Protocol

被引:2
|
作者
Zhou, Rui [1 ]
Min, Rong [1 ]
Yu, Qi [1 ]
Li, Chanjuan [1 ]
Sheng, Yong [1 ]
Zhou, Qingguo
Wang, Xuan [2 ]
Li, Kuan-Ching [3 ]
机构
[1] Lanzhou Univ, Sch Informat Sci & Engn, Lanzhou 730000, Peoples R China
[2] Lanzhou Univ Technol, Sch Sci, Lanzhou 730050, Gansu, Peoples R China
[3] Providence Univ, Dept Comp Sci & Informat Engn CSIE, Taichung, Taiwan
关键词
Safe Node Sequence Protocol; fault-tolerance; event-triggered protocol; model checking; SYSTEM; MODEL;
D O I
10.1109/AINA.2014.99
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Fault-tolerance has huge impact on embedded safety-critical systems. As technology that assists to the development of such improvement, Safe Node Sequence Protocol (SNSP) is designed to make part of such impact. In this paper, we present a mechanism for fault-tolerance and recovery based on the Safe Node Sequence Protocol (SNSP) to strengthen the system robustness, from which the correctness of a fault-tolerant prototype system is analyzed and verified. In order to verify the correctness of more than thirty failure modes, we have partitioned the complete protocol state machine into several subsystems, followed to the injection of corresponding fault classes into dedicated independent models. Experiments demonstrate that this method effectively reduces the size of overall state space, and verification results indicate that the protocol is able to recover from the fault model in a fault-tolerant system and continue to operate as errors occur.
引用
收藏
页码:813 / 820
页数:8
相关论文
共 50 条
  • [1] Formal Verification of Fault-Tolerant Hardware Designs
    Entrena, Luis
    Sanchez-Clemente, Antonio J.
    Garcia-Astudillo, Luis A.
    Portela-Garcia, Marta
    Garcia-Valderas, Mario
    Lindoso, Almudena
    Sarmiento, Roberto
    [J]. IEEE ACCESS, 2023, 11 : 116127 - 116140
  • [2] FAULT-TOLERANT PROCESSOR EVALUATION EXPERIENCE - FORMAL VERIFICATION STUDIES
    KLJAICH, J
    SMITH, BT
    WOJCIK, AS
    [J]. TRANSACTIONS OF THE AMERICAN NUCLEAR SOCIETY, 1985, 49 (JUN): : 379 - 379
  • [3] FORMAL VERIFICATION FOR FAULT-TOLERANT ARCHITECTURES - PROLEGOMENA TO THE DESIGN OF PVS
    OWRE, S
    RUSHBY, J
    SHANKAR, N
    VONHENKE, F
    [J]. IEEE TRANSACTIONS ON SOFTWARE ENGINEERING, 1995, 21 (02) : 107 - 125
  • [4] Formal verification of fault-tolerant software design: the CSP approach
    Yeung, WL
    Schneider, SA
    [J]. MICROPROCESSORS AND MICROSYSTEMS, 2005, 29 (05) : 197 - 209
  • [5] Data Recovery Approach for Fault-Tolerant IoT Node
    Vedavalli, Perigisetty
    Deepak, Ch
    [J]. INTERNATIONAL JOURNAL OF ADVANCED COMPUTER SCIENCE AND APPLICATIONS, 2022, 13 (01) : 768 - 774
  • [6] Construction and Formal Verification of a Fault-Tolerant Distributed Mutual Exclusion Algorithm
    Shishkin, Evgeniy
    [J]. PROCEEDINGS OF THE 16TH ACM SIGPLAN INTERNATIONAL WORKSHOP ON ERLANG (ERLANG '17), 2017, : 1 - 12
  • [7] Using Formal Verification to Reduce Test Space of Fault-tolerant Programs
    Xavier, Kleber S.
    Hanazumi, Simone
    de Melo, Ana C. V.
    [J]. SEFM 2008: SIXTH IEEE INTERNATIONAL CONFERENCE ON SOFTWARE ENGINEERING AND FORMAL METHODS, PROCEEDINGS, 2008, : 181 - 190
  • [8] Systematic formal verification for fault-tolerant time-triggered algorithms
    Rushby, J
    [J]. IEEE TRANSACTIONS ON SOFTWARE ENGINEERING, 1999, 25 (05) : 651 - 660
  • [10] Verification of Fault-Tolerant Protocols with Sally
    Dutertre, Bruno
    Jovanovic, Dejan
    Navas, Jorge A.
    [J]. NASA FORMAL METHODS, NFM 2018, 2018, 10811 : 113 - 120