HMCSP: Reducing Transaction Latency of CSR-based SPMV in Hybrid Memory Cube

被引：1

作者：

Qian, Cheng ^{[1
]}

Childers, Bruce ^{[2
]}

Huang, Libo ^{[1
]}

Yu, Qi ^{[1
]}

Wang, Zhiying ^{[1
]}

机构：

[1] Natl Univ Def Technol, Changsha, Hunan, Peoples R China

[2] Univ Pittsburgh, Pittsburgh, PA 15260 USA

来源：

2018 IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND SOFTWARE (ISPASS) | 2018年

关键词：

D O I：

10.1109/ISPASS.2018.00021

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Sparse Matrix Multiplication Vector (SPMV) plays a significant role in sparse linear algebra. Based on the high parallelization of matrix multiplication, SPMV has been accelerated with GPUs, Intel MIC, and FPGAs. The Micron Hybrid Memory Cube (HMC) is a highly parallel device that has atomic operations which support processing in memory (PIM). In this paper, we propose HMCSP, which extends the HMC's existing PIM capability to reduce the memory transaction latency of SPMV. By taking advantage of atomic operations and data prefetch, HMCSP reduces memory transaction latency of SPMV by 49.7% compared to a conventional HMC.

引用

页码：114 / 116

页数：3

共 10 条

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