Hierarchical test compression for SoC designs

For SOC designs, it becomes very desirable to have IP blocks that come with their own test compression while having a second level of compression at the full-chip level. If done without careful analysis, this second-level compression logic can be subject to much greater aliasing and error masking because of the presence of X (unknown) values. This article presents a systematic way of designing the second-level compression logic. This method preserves the same X and multiple-error tolerance as the original X-Compact. The new method also successfully handles the use of identical cores, where there is a far higher chance of multiple errors and X values. © 2008 IEEE.