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Demonstration of intrinsic STDP learning capability in all-2D multi-state MoS2 memory and its application in modelling neuromorphic speech recognition
被引:7
|作者:
Paul, Tathagata
[1
]
Mukundan, Akshaya A.
[2
]
Tiwari, Krishna Kanhaiya
[3
]
Ghosh, Arindam
[1
,4
]
Thakur, Chetan Singh
[2
]
机构:
[1] Indian Inst Sci, Dept Phys, Bangalore 560012, Karnataka, India
[2] Indian Inst Sci, Dept Elect Syst Engn, Bangalore 560012, Karnataka, India
[3] Visva Bharati Univ Santiniketan, Santini Ketan 731235, W Bengal, India
[4] Indian Inst Sci, Ctr Nanosci & Engn, Bangalore 560012, Karnataka, India
来源:
关键词:
neuromorphic computing;
electronic cochlea;
brain-inspired learning;
emerging devices;
beyond CMOS;
MoS2;
memristors;
SYNAPTIC TRANSISTOR;
GRAPHENE;
DEVICE;
HETEROSTRUCTURES;
D O I:
10.1088/2053-1583/ac210a
中图分类号:
T [工业技术];
学科分类号:
08 ;
摘要:
The human brain can be characterized by its large number of adaptive synapses, connecting billions of neurons capable of both learning and perceiving the environment. Neuromorphic computing, based on brain-inspired principles, is a promising technology, to build low-power, distributed, fault-tolerant intelligent systems mainly for perception tasks. Here, we demonstrate the intrinsic capability of floating gate (FG) MoS2 device (MoS2 FG-FET) to model the spike time dependent plasticity (STDP) learning rule that is based on the transient response of the MoS2 channel to spikes applied to the source and gate leads. We implemented the STDP learning protocol in a neuromorphic speech recognition system (NSRS), inspired by the human auditory pathway, for various auditory recognition tasks. Our proposed NSRS consists of a cochlea model, an unsupervised feature learning stage, and a simple linear classifier. The unsupervised learning stage uses the biologically plausible STDP learning in novel two-dimensional MoS2 FG-FET memory which circumvents the requirement of any other learning circuitry. Demonstration of STDP modelling in two-dimensional (2D) MoS2 is an important step towards incorporating 2D architectures for reduced device footprints in neuromorphic learning circuits.
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