A low power pipelined analog-to-digital converter using series sampling capacitors

被引：0

作者：

Cho, SH ^{[1
]}

Ock, S ^{[1
]}

Lee, SH ^{[1
]}

Lee, JS ^{[1
]}

机构：

[1] Korea Adv Inst Sci & Technol, Taejon, South Korea

来源：

2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS | 2005年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A low power pipelined analog-to-digital converter(ADC) that employs sampling capacitors connected in series is presented. The series sampling capacitors minimize the size of the sampling capacitors to the KT/C limit without degrading the ADC's performance due to mismatch. Using this technique, a 10-bit 100MHz pipelined ADC is designed and simulated. The ADC achieves 60dB of signal-to-noise-and-distort ion ratio(SNDR) at 100MHz while consuming 47mW from 1.8-V supply in 0.18 mu m CMOS technology.

引用

页码：6178 / 6181

页数：4

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